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DFT / Senior DFT Engineer – Semiconductor Design Engineering - iTest Bangladesh Limited

iTest Bangladesh Limited
Dhaka (Mohakhali)
Full TimeNot specifiedBdJobsActive Hiring

Salary

Negotiable

Deadline

26 May 2026

Source

BdJobs

Location

Dhaka (Mohakhali)

72%

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Salary

Negotiable

Deadline

26 May 2026

Key Responsibilities

* Spearhead the development and implementation of Memory BIST (MBIST) solutions using Tessent tools, driving configuration, validation, and optimization. * Architect and validate test patterns, ensuring seamless integration with Automated Test Equipment (ATE) platforms and resolving debugging challenges. * Analyze and interpret silicon data to identify test failures, informing coverage and yield enhancements. * Design and integrate Design-for-Test (DFT) structures, leveraging Verilog to create scan, MBIST, and other essential components. * Collaborate with cross-functional teams to verify DFT logic at both RTL and gate levels, ensuring accuracy and precision. * Drive DFT implementation and closure by working closely with synthesis and physical design teams, streamlining the design flow. * Contribute to DFT planning, insertion, and sign-off activities, providing expert guidance and support. * Troubleshoot and resolve issues across the entire design flow, from RTL to silicon, to ensure timely and successful project delivery.

Requirements

Experience

3 to 5 years

Skills

DFTVLSI DesignTessent (Mentor/Siemens) tool suiteMemory BIST (MBIST) architectureVerilog/SystemVerilogATESilicon debug (SI analysis)SoC-level DFT integrationTiming closurePhysical-aware DFTSynthesisPhysical design flows (PnR)Scripting (Tcl/Python)

Education

  • B.Sc/M.Sc in EEE, EE, CSE

Additional Requirements

  • 3–5 years of experience in DFT / VLSI Design
  • Strong hands-on experience with Tessent (Mentor/Siemens) tool suite
  • Expertise in Memory BIST (MBIST) architecture and implementation
  • Experience in pattern generation, validation, and tester bring-up
  • Proficiency in Verilog/SystemVerilog for DFT/test logic
  • Good understanding of scan, ATPG, and DFT methodologies
  • Experience working with ATE and silicon debug (SI analysis)
  • Experience with SoC-level DFT integration
  • Familiarity with timing closure and physical-aware DFT
  • Strong debugging and problem-solving skills
  • Familiarity with synthesis and physical design flows (PnR)
  • Knowledge of scripting (Tcl/Python)

Compensation & Benefits

Mobile billWeekly 2 holidaysMedical allowanceT/ALunch Facilities: Full SubsidizeSalary Review: YearlyFestival Bonus: 2Transportation Facility/ Pick & DropEarned Leave EncashmentLunch Facilities: Full Free

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