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DFT Engineer or Senior DFT Engineer - Engineering - iTest Bangladesh Limited

M & J Group
Dhaka (Mohakhali)
Full TimeNot specifiedBdJobsActive Hiring

Salary

Negotiable

Deadline

19 May 2026

Source

BdJobs

Location

Dhaka (Mohakhali)

Salary

Negotiable

Deadline

19 May 2026

Key Responsibilities

* Spearhead the development and implementation of Memory BIST (MBIST) solutions using Tessent tools, driving configuration, validation, and optimization. * Architect and validate test patterns, ensuring seamless integration with ATE platforms and resolving debugging challenges to achieve high test coverage. * Analyze and interpret silicon data to identify and rectify test failures, enhancing overall yield and product quality. * Design and integrate Design-for-Test (DFT) structures, including scan and MBIST, using Verilog to ensure efficient testability and manufacturability. * Collaborate with cross-functional teams to verify DFT logic at both RTL and gate levels, guaranteeing accurate implementation and functionality. * Drive DFT implementation and closure by working closely with synthesis and physical design teams, ensuring a smooth and efficient design flow. * Contribute to DFT planning, insertion, and sign-off activities, providing expert guidance and support to ensure project goals are met. * Troubleshoot and resolve issues across the entire design flow, from RTL to silicon, to ensure high-quality products and rapid time-to-market.

Requirements

Skills

DFTVLSI DesignTessent (Mentor/Siemens) tool suiteMemory BIST (MBIST) architectureVerilog/SystemVerilogATESoC-level DFT integrationSynthesisPhysical design flows (PnR)Tcl/Python scripting

Education

  • B.Sc/M.Sc in EEE, EE, CSE

Additional

  • 3–5 years of experience in DFT / VLSI Design
  • Strong hands-on experience with Tessent (Mentor/Siemens) tool suite
  • Expertise in Memory BIST (MBIST) architecture and implementation
  • Experience in pattern generation, validation, and tester bring-up
  • Proficiency in Verilog/SystemVerilog for DFT/test logic
  • Good understanding of scan, ATPG, and DFT methodologies
  • Experience working with ATE and silicon debug (SI analysis)
  • Experience with SoC-level DFT integration
  • Familiarity with timing closure and physical-aware DFT
  • Strong debugging and problem-solving skills
  • Familiarity with synthesis and physical design flows (PnR)
  • Knowledge of scripting (Tcl/Python)

Compensation & Benefits

Mobile billWeekly 2 holidaysMedical allowanceT/ALunch Facilities: Full SubsidizeSalary Review: YearlyFestival Bonus: 2Transportation Facility/ Pick & DropEarned Leave EncashmentLunch Facilities: Full Free

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