Intern-RTL Design & Verification Engineering

* Drive the development of cutting-edge semiconductor designs by participating in comprehensive training programs and technical workshops on RTL design and verification. * Collaborate with senior engineers to architect and implement RTL designs, translating requirements into functional implementations and verification environments. * Design and develop SystemVerilog RTL code, capture schematics, and create UVM-based testbenches to fuel innovative silicon projects. * Lead quality improvement efforts by actively engaging in design reviews, code reviews, and verification reviews, and incorporating feedback to refine designs. * Spearhead debugging activities, regression testing, and coverage analysis to ensure seamless design functionality. * Manage technical documentation, including design descriptions, verification plans, and test reports, to maintain transparency and knowledge sharing. * Identify and track issues, communicating findings clearly and adhering to disciplined engineering practices to drive resolution. * Stay at the forefront of industry trends by continuously updating knowledge of industry tools, standards, and best practices in digital design and verification.